The present invention relates to memory devices, and in particular, to a reading circuit of the voltage-sensing type for reading non-volatile memory cells in a memory device.
The storage of a data in digital form in a non-volatile memory cell such as, for example, a flash electrically erasable programmable read-only memory (EEPROM) cell takes place by suitable programming of the threshold voltage of the cell. The need to use memory devices with ever higher capacities has made multilevel memories particularly advantageous. Theoretically, in a multilevel memory, the threshold voltage of a cell of the memory can be programmed not merely to one of two possible levels (as is the case for two-level cells) but to one of 2nxe2x88x921 levels, enabling n bits to be stored in a single cell.
Two different techniques are known for reading the data stored in a memory cell. According to one of these techniques, known as current sensing, the reading is performed while the voltages applied to the drain, to the source, and to the gate of the memory cell to be read are kept constant and at a suitable value. In similar conditions of biasing, the cell addressed will therefore absorb a drain current which depends on its programming state.
In contrast, the other reading technique, which is known as voltage sensing, provides for the reading to be performed while the drain current absorbed by the cell addressed is kept constant and the biasing conditions at the drain and source terminals are fixed. In particular, voltage sensing takes place by acting on the gate voltage to force the memory cell to absorb a predetermined current. The threshold voltage programmed in the cell, which is unequivocally correlated with the gate voltage, can be determined by evaluating the gate voltage which brings the cell to absorb this current in steady-state conditions, and thus deriving the data stored in the cell. In one of its possible forms, this reading technique requires a control circuit which regulates the gate voltage applied to the cell in order for the cell to absorb the predetermined current.
U.S. Pat. No. 6,034,888 describes a voltage sensing reading circuit in which a negative feedback circuit is used. The feedback circuit comprises an operational amplifier which receives the drain voltage of the memory cell to be read at a non-inverting input, and a biasing voltage at an inverting input. This operational amplifier outputs the voltage to be applied to the gate terminal of the cell. The times required to reach a steady state, which are indicated in the patent, may be 1 xcexcs or 500 ns, according to the particular circuit configuration. Moreover, in this patent, it is pointed out that the node (indicated by the numeral 16) of the feedback circuit described with reference to FIG. 1, therein which connects the non-inverting input of the operational amplifier to the drain terminal of the memory cell, may cause instability in the reading circuit.
The instability of the reading circuit formed in accordance with this patent is attributable to the presence of high-impedance nodes to which low-frequency poles of the transfer function of the feedback circuit correspond. This instability represents a considerable disadvantage, since it necessitates the use of additional compensation circuits which, as well as making the circuit configuration complex, brings about an increase in the reading times. That is, there is an increase in the time taken to reach the steady state in which the data programmed in the cell is evaluated.
Moreover, it is pointed out that the above mentioned patent does not address problems connected with power consumption by the circuit.
In the construction of integrated devices in semiconductor chips, such as memories, there is a tendency to reduce the supply voltage by bringing it down, for example, to values of 3 V or 1.8 V. This tendency conflicts with the need, which is characteristic of reading circuits in the multilevel context, to supply the memory cell to be read with a gate voltage greater than that of the supply in order to interact correctly with the cell.
This need is thus pressing for multilevel cells, since a widening of the range of voltages applicable to the gate terminal of the memory cell renders the discrimination of the threshold programmed among a number of possible values, which is required to be as high as possible, less critical. In order to supply sufficiently high voltages, conventional reading circuits make use of integrated positive voltage-booster devices.
It is pointed out that, in order to read memories with a large number of cells, the area in the semiconductor chip intended for the positive voltage-boosters and the power absorbed thereby, may become considerable. It is therefore essential to provide reading circuits for which the dimensions and/or the number of positive voltage-boosters used is limited.
In view of the foregoing background, an object of the present invention is to provide a reading circuit for reading memory cells which does not have the disadvantages indicated above with reference to conventional reading circuits.
This and other objects, advantages and features are achieved by a reading circuit for reading a non-volatile memory cell having an output terminal for an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit comprises a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current.
The feedback circuit comprises current-amplification means having a first terminal for receiving a current error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.